In the context of the application outlined previously, an example structure is defined as a “circular FIFO micro-architecture” according to the arrangement represented schematically in FIG. 1. This is basically a symmetrical structure, in which a certain number of memory locations is present, designed to receive input data (data in) and to return them at output (data out). The block diagram in FIG. 1 basically represents the structure of the datapath, where the representation of the control function has been omitted for simplicity.
Referring to a purposely simple model in order not to render the treatment excessively complex, a structure comprising three memory locations 101, 102, 103 may be considered, in which the input data are written with a write interface 104 under the control of an input or write pointer (write ptr) and are then read at output with a read interface 105, resorting to a read pointer (read ptr).
Hence, in the case of the structure represented in FIG. 1, it is a symmetrical structure in which the write and read pointers control access to the FIFO buffer for the operations of writing and reading, respectively. In a structure of this sort, there is no dependence between the updatings of the pointers, in the sense that a write operation entails updating only of its respective pointer. The same applies also to the read function, whereas to manage the limit cases of an empty buffer and a full buffer it is possible to refer to a control logic.
In this solution the input data, coming from the write interface, can be guided to any of the memory locations with the write pointer that chooses the location in which to store the input data. This means that the single lane of the datapath presents a so-called “fanout” (i.e., a number of terminal ports to be driven) that is rather high, determined by the number of locations that are to be driven.
An even worse situation arises in the case of the control signal (referred to as “write enable”), which derives in a combinational way from the signals for control of interface flow (write request, write grant). When there is a write operation, said control signal must in fact drive not only the locations of the FIFO buffer, for enabling the one that has been selected by the write pointer, but also all the functional multiplexers that select each bit of the location (the number of which depends evidently upon the size of the memory location).
From a design and implementation standpoint, high fanout values imply the presence of considerable capacitive loads on the paths of the control data signals (datapath/control), which results in a degradation of their timing properties, such as for example the transition time.
As a remedy to possible violations, the tools for design and synthesis of digital circuits (to which this function is normally entrusted) use a technique consisting of automatic building of a tree network with technological cells having buffer functions for generating a number of copies of the same input signal and dividing the overall fanout between them.
This solution is schematically presented in FIG. 2, where appearing on the left is the fanout structure and on the right the corresponding tree structure of buffer cells on a generic number n of levels.
In the implementation step, if recourse is had to the solution referred to herein, on the write signals a delay is introduced due to their propagation through the elementary buffer cells provided for solving the problem of fanout. It is, in other words, a sort of implementation delay that must be distinguished from the delay introduced by the functional logic and that is due to the cells inserted as a remedy to the possible violations of the design rules.
FIG. 3 hence corresponds to the practical implementation of the scheme represented in general terms in FIG. 1 where in fact there may be noted the memory locations of the buffer 101, 102, 103 (that will be assumed organized on N bits) with the representation in greater detail of the write section or interface 104, which comprises trees of the buffer 104a that are to receive on the one hand the input data (data in) and on the other, starting from a logic 106, the control signals corresponding to the control signal (write enable), to the write pointer, and to the action of control of the logic 106 exerted by a finite-state machine (FSM). In the same FIG. 3 the references 104b designate the functional multiplexers that select the bits of the various locations 101, 102, 103 (and the number of which depends evidently upon the size, i.e., upon the number N of bits, of said memory location).
FIGS. 4 and 5 refer to a micro-architecture constituting an improvement to the solution described previously with reference to FIGS. 1 to 3. The solution of FIGS. 4 and 5 can be defined as a fast-write FIFO micro-architecture, in which the performance of the signals of the datapath are improved by enabling writing only in a single write location selected, thus avoiding having to guide the input signals towards different memory locations of the FIFO buffer.
For example, the aforesaid single write location can be the location “0”, designated by 101 in the figures, even though as single write location it would be possible to choose a different location.
As may be appreciated from a direct comparison of FIGS. 1 and 3, on the one hand, and of FIGS. 4 and 5, on the other, where in all these figures the same references are used to designate entities that are identical or equivalent to one another, the solution of FIGS. 4 and 5 does without the write pointer on the write side, whereas the read pointer remains (with the corresponding interface 105) on a read side.
The structure of FIG. 4 is clearly asymmetrical, and for managing the write operation on a single location kept fixed (for example, the location “0” designated by 101) an operation of shift of all the other locations (102 and 103, in the example considered herein) of the FIFO structure is envisaged. With reference to the location “0” as write location, these operations of shift are in general operations of “shift up”, carried out whenever there is a new writing operation so as to prevent the data previously written from being overwritten.
Accordingly, it is envisaged to update the read pointer thus selecting (according to the FIFO logic) the “oldest” data that have not yet been read. This operating mode enables a correct propagation of the data to the reading side, without any loss of information.
In brief, the solution to which FIGS. 4 and 5 refer bases its operation on the criterion of:
writing the data D1, D2 at input to the memory in a single write location (the location 101, in the example considered herein) from among the plurality of locations 101, 102, 103 of the memory; and
making the (single) write location 101 available for writing an input datum with a shift of the datum previously written in said single write location 101 to another of the locations 101, 102, 103 of the memory.
The corresponding implementation, schematically illustrated in FIG. 5, presents as a main advantage the fact of eliminating the dependence of the input datapath (data in) upon the fanout deriving from the number of locations. In practice, in the solution of FIGS. 4 and 5, there are no violations at the level of transition of the signals deriving from high capacitive loads so that there is no degradation of the levels of performance in terms of timing deriving from the insertion of the tree of the buffer-cell network described previously.
The solution of FIGS. 4 and 5 does not, however, solve the problem regarding the write control path linked to the fact that the write-enable signal (write enable) must drive all the locations so as to enable writing of the new data and, in addition, simultaneous shifting of all the locations in order to prevent overwriting. This signal hence still has a number of cells to be driven that depends upon the number of the locations of the FIFO structure and upon the size of said locations.
Once again, at the level of design and synthesis of the circuit, it is necessary to insert a tree structure of the buffer cells as a remedy to the violations of fanout, which has an adverse impact on the timing performance of the corresponding micro-architecture as regards the control part of the write interface.
This situation is highlighted in FIG. 5 where it may be noted that the write-enable signal must in any case drive the logic 106 and, through the network of buffer cells 104, the functional multiplexers 104b to guarantee the write operation in a correct way and the consistency of the data already stored in the memory locations.
A solution such as the one illustrated in FIGS. 4 and 5 proves satisfactory with datapaths that are critical in terms of timing on the write side, but not with a dataflow-control path that is critical from the standpoint of timing given that the write-enable signal is in the last resort a combinational result thereof.
From what has been outlined previously, it emerges that FIFO buffer structures of the type described above, with flow-control capacities, do not present ideal modalities of operation, moreover if, for example, the critical aspects of timing are considered, which, above all, do not normally appear evident at an architectural level when the allocation and sizing of the memory locations is defined according to the design targets, but emerge, instead, during the implementation step, when design-dependent variables (fanout, capacitive load, transition time, propagation delay) are taken into account, and are such that the dimensions of the FIFO buffer (expressed in terms of number of locations and size in bits of the individual location) can produce misalignments in the timing performance in practice achieved as compared to the performance expected in the design stage.
The object of the invention is to provide a solution that will be able to overcome said drawbacks.